When manufacturing a semiconductor device, an insulating layer is typically formed after formation of a gate, and metal contact holes for exposing source/drain regions are then formed by an etching process. After that, the contact holes are filled with a conductive material to form contact plug structures.
With the rapid development of semiconductor manufacturing procedure and/or process, characteristic dimensions of devices continue to reduce, and contact dimension (i.e. contact diameter) is scaled down, so as to ensure that the contact will not cause a short circuit between source/drain diffusion regions and the gate. However, scaling down the contact size significantly increases contact resistance and makes it difficult to form the contact. Moreover, the gate may be exposed during the process of etching the contact holes, especially in a case of misalignment. Consequently, shorts may occur between the gate and the contact plugs.
In view of this, there is a need to provide a novel semiconductor structure and a method for manufacturing the same, which can reduce the contact resistance and suppress or avoid the shorts, while simplifying manufacturing process and lowering manufacture cost.